1. Technical Field
The present invention relates to semiconductor devices and processing, and more particularly to transistor structures employing a SiC channel layer and a bonded gate structure.
2. Description of the Related Art
SiC is used extensively for high voltage applications. However, formation of a thick gate stack on SiC for high-voltage applications is challenging. SiC oxidation is a very long and high temperature process and leads to the segregation of the carbon atoms in the channel. Typical interface trap density (Dit) or fixed charge numbers for oxide formed on SiC is in 1×1012 cm−2 range, nearly two orders of magnitude higher than thermal oxide on Si. For high-voltage applications, the gate dielectric should be sufficiently thick to sustain large vertical electric fields. Furthermore, the presence of positive fixed charge leads to reliability issues such as threshold voltage instability under electrical or thermal stress. This therefore hinders the feasibility of thick high-k dielectrics for high-voltage SiC transistors.